1. Prime Number List

Figure2 – typical implementation architecture of a rising edge detector. Using the architecture in Figure2, we can generate a pulse of one clock, no matter how long is the input control signal, so every time we push the button we will count +1. VHDL implementation of an edge-detector. A possible VHDL implementation is.

Prime Number List

Level vs edgeIn digital synchronous design sometimes we need to detect the transition ‘0’-’1′ or ‘1’-’0’ of a signal.As a simple example, suppose you have a counter with enable input port connected to an external push button. You need to count +1 every time you push the button. Figure1 – example of human generated pulse used to enable a counterLet the counter clock to be for example 50 MHz. The clock period is 20 ns. In the simulation of is clear that the circuit generates a pulse of only one clock cycle, no matter how long is the control signal. Figure3 – VHDL code simulation of rising edge detectorTypical mistake in edge detector implementationSurfing the web, you can find many examples of rising edge detector as reported in.

Figure4 – typical mistake of rising edge detector implementationThis implementation contains a big mistake.Let see a simulation of this circuits. As you can see, if the edge of the input signal is very close to the internal clock edge the pulse generated is very short as shown in Figure5 and Figure6.

Moreover, it is possible to lose the detection due to the internal physical delay of the circuit. Figure5 – simulation detail of a wrong implementation of an edge detector Figure6 – simulation detail of a wrong implementation of an edge detectorSo, when you have to interface asynchronous domain with a synchronous one you shall put a first sampling stage before implementing any combinatorial operation.As a general rule, to minimize, a possible solution is to put 2 register stage before any combinatorial operation.As a drawback, this solution will introduce a delay of one clock cycle in the output of the circuits.If you appreciated this post, please help us to share it with your friend. I appreciated your article as a beginner in vhdl, however I think it could have been made much clearer.Two pedagogical mistakes:– The vhdl code does not correspond strictly to the preceding diagram. When reading the code for the first time we cannot help wonder what is this reset doing there?It just disturbs our mind which is focused on the main issue of the post.In addition having the same signal names than in the diagram would also help a lot.– Later on you show us a typical mistake found on other sites.

My first thouht is why the heck removing the inverter and using the /Q output should not work?I realized later that you also made another change: you removed the first register and apparently that is the (only?) reason why the circuit does not work.But at the end of the article we still do not know if having only removed the inverter and using /Q could have caused any problems! Hi, thank you for your feedback!In the post, I do not use /Q because the code is RTL code.As you can see “ not r1input” in the RTL code is definitely R1inputinv.Moreover, it can be view as /Q.The post would report a possible VHDL/RTL implementation of an edge-detector.If you write a structural VHDL code using a Flip-Flop component with a /Q output you can avoid the use if the inverter.The mistake is not the use of the inverter,but the missing of the first flip-flop as you can see in Figure 5 where the edge is not detected.I hope I answered your doubtsCiao.

Thank you for the post, it was an interesting read! However, I’m a bit sceptical to the section “Typical mistake in edge detector implementation”. Either the input signal is asynchronous, in which case both circuits suffer from metastability issues, or the input signal is synchronous, in which case either of the two circuits are fine depending on the use case.

The second design may be favorable if you know that the pulse will last long enough for your needs, since less hardware is required and since it decreases the latency of that path (which e.g. Is the need here: ). Meanwhile, the added register in the first circuit may be a possible solution if the pulse doesn’t last long enough.

I’m new to hardware design and would very much like to know your opinion on this.

VHDL samples VHDL samplesThe sample VHDL code contained below is for tutorial purposes.An expert may be bothered by some of the wording of the examplesbecause this WEB page is intended for people just starting tolearn the VHDL language. There is no intention of teachinglogic design, synthesis or designing integrated circuits.It is hoped that people who become knowledgeable of VHDL willbe able to develop better models and more rapidly meet whatevertheir objectives might be using VHDL simulations.A few VHDL compilers have bugs.